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19-1016; Rev 2; 2/96
CMOS, Quad, Serial-Interface 8-Bit DAC
_______________General Description
The MAX500 is a quad, 8-bit, voltage-output digital-toanalog converter (DAC) with a cascadable serial interface. The IC includes four output buffer amplifiers and input logic for an easy-to-use, two- or three-wire serial interface. In a system with several MAX500s, only one serial data line is required to load all the DACs by cascading them. The MAX500 contains double-buffered logic and a 10-bit shift register that allows all four DACs to be updated simultaneously using one control signal. There are three reference inputs so the range of two of the DACs can be independently set while the other two DACs track each other. The MAX500 achieves 8-bit performance over the full operating temperature range without external trimming.
____________________________Features
o Buffered Voltage Outputs o Double-Buffered Digital Inputs o Microprocessor and TTL/CMOS Compatible o Requires No External Adjustments o Two- or Three-Wire Cascadable Serial Interface o 16-Pin DIP/SO Package and 20-Pin LCC o Operates from Single or Dual Supplies
MAX500
______________Ordering Information
TEMP. RANGE PIN-PACKAGE ERROR (LSB) PART MAX500ACPE 0C to +70C 16 Plastic DIP 1 MAX500BCPE MAX500ACWE MAX500BCWE MAX500BC/D MAX500AEPE MAX500BEPE MAX500AEWE MAX500BEWE MAX500AEJE MAX500BEJE MAX500AMJE MAX500BMJE MAX500AMLP MAX500BMLP 0C to +70C 0C to +70C 0C to +70C 0C to +70C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C -55C to +125C -55C to +125C -55C to +125C 16 Plastic DIP 16 Wide SO 16 Wide SO Dice* 16 Plastic DIP 16 Plastic DIP 16 Wide SO 16 Wide SO 16 CERDIP 16 CERDIP 16 CERDIP 16 CERDIP 20 LCC 20 LCC 2 1 2 2 1 2 1 2 1 2 1 2 1 2
________________________Applications
Minimum Component Count Analog Systems Digital Offset/Gain Adjustment Industrial Process Control Arbitrary Function Generators Automatic Test Equipment
________________Functional Diagram
SRO VREFC AGND DGND VSS VDD LDAC VREFA/B VREFD
VOUTA INPUT REG A DAC REG A DAC A
*Contact factory for dice specifications.
_________________Pin Configurations
VOUTB
TOP VIEW
V OUT B 1 16 V OUT C 15 V OUT D 14 V DD
DATA BUS
10/11BIT SHIFT REGISTER
INPUT REG B
DAC REG B
DAC B
VOUTC INPUT REG C DAC REG C DAC C
V OUT A 2 V SS 3 V REF A/B 4
MAX500
13 VREFC 12 V REF D 11 SRO 10 SCL 9 LOAD
VOUTD INPUT REG D CONTROL LOGIC DAC REG D DAC D
AGND 5 DGND 6 LDAC 7
MAX500
SDA 8
LOAD SDA SCL
DIP/SO
Pin Configurations continued on last page.
________________________________________________________________ Maxim Integrated Products 1
For free samples & the latest literature: http://www.maxim-ic.com, or phone 1-800-998-8800
CMOS, Quad, Serial-Interface 8-Bit DAC MAX500
ABSOLUTE MAXIMUM RATINGS
Power Requirements VDD to AGND...........................................................-0.3V, +17V VDD to DGND ..........................................................-0.3V, +17V VSS to DGND ..................................................-7V, (VDD + 0.3V) VDD to VSS ...............................................................-0.3V, +24V Digital Input Voltage to DGND ....................-0.3V, (VDD + 0.3V) VREF to AGND .............................................-0.3V, (VDD + 0.3V) VOUT to AGND (Note 1)...............................-0.3V, (VDD + 0.3V) Power Dissipation (TA= +70C) Plastic DIP (derate 10.53mW/C above +70C) ............842mW Wide SO (derate 9.52mW/C above +70C)................762mW CERDIP (derate 10.00mW/C above +70C) ...............800mW LCC (derate 9.09mW/C above +70C).......................727mW Operating Temperature Ranges MAX500_C_ _ ....................................................0C to + 70C MAX500_E_ _...................................................-40C to +85C MAX500_M_ _ ................................................-55C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10sec) .............................+300C
Note 1: The outputs may be shorted to AGND, provided that the power dissipation of the package is not exceeded. Typical short-circuit current to AGND is 25mA
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS--Dual Supplies
(VDD = +11.4V to +16.5V, VSS = -5V 10%, AGND = DGND = 0V, VREF = +2V to (VDD - 4V), TA = TMIN to TMAX, unless otherwise noted.) PARAMETER STATIC PERFORMANCE Resolution Total Unadjusted Error Relative Accuracy Differential Nonlinearity Full-Scale Error Full-Scale Tempco VDD = 15V 5%, VREF = 10V MAX500A MAX500B Guaranteed monotonic MAX500A MAX500B VREF = 10V TA = +25C Zero-Code Error TA = TMIN to TMAX Zero-Code Tempco REFERENCE INPUT Reference Input Range Reference Input Resistance Reference Input Capacitance Channel-to-Channel Isolation AC Feedthrough DIGITAL INPUTS Digital Input High Voltage Digital Input Low Voltage Digital Output High Voltage Digital Output Low Voltage Digital Input Leakage Current Digital Input Capacitance 2 VIH VIL VOH VOL IOUT = -1mA, SRO only IOUT = 1mA, SRO only (Note 4) TA = +25C (Note 2) Excluding LOAD LOAD = 0V VDD - 1 0.4 1 30 8 VREFC, VREFD VREFA/B TA = +25C, code dependent (Note 2) TA = +25C (Notes 2, 3) TA = +25C (Notes 2, 3) 2 11 5.5 -60 -70 2.4 5.5 0.8 MAX500A MAX500B MAX500A MAX500B 30 VDD - 4 MAX500A MAX500B 8 1 2 1/2 1 1 1/2 1 5 15 20 20 30 Bits LSB LSB LSB LSB ppm/C SYMBOL CONDITIONS MIN TYP MAX UNITS
mV
V/C V k 100 pF dB dB V V V V A pF
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CMOS, Quad, Serial-Interface 8-Bit DAC
ELECTRICAL CHARACTERISTICS--Dual Supplies (continued)
(VDD = +11.4V to +16.5V, VSS = -5V 10%, AGND = DGND = 0V, VREF = +2V to (VDD - 4V), TA = TMIN to TMAX, unless otherwise noted.) PARAMETER DYNAMIC PERFORMANCE Voltage Output Slew Rate VOUT Settling Time Digital Feedthrough Digital Crosstalk Output Load Resistance Positive SUPPLIES POWER Supply Voltage Positive Supply Voltage Positive Supply Current VDD VDD IDD ISS TA = +25C (Note 2) To 1/2LSB, VREF = 10V, VDD = +15V, 2k in parallel with 100pF load (Note 2) (Note 5) (Note 5) VOUT = 10V For specified performance For specified performance Outputs unloaded TA = +25C TA = TMIN to TMAX TA = +25C TA = TMIN to TMAX 150 150 0 350 350 (Note 7) (Note 7) tLDW tLDS tLDAC tD1 t1 tH t1 t2 (Note 7) (Note 7) tLDAC tS1 tS2 tS3 tD1 CLOAD = 50pF Start condition Stop condition 150 150 100 125 150 CLOAD = 50pF 350 0 350 350 50 50 150 150 150 150 50 50 2 11.4 11.4 16.5 16.5 10 12 -9 -10 3 8 2.5 50 50 4.5 V/s s nV-s nV-s k V V mA SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX500
Negative Supply Current
Outputs unloaded
mA
SWITCHING CHARACTERISTICS (TA = +25C, Note 6) 3-Wire Mode SCL Setup SDA Valid to SDA Valid to SCL Setup SDA Valid to SCL Hold SCL High Time SCL Low Time SCL Rise Time SCL Fall Time LOAD Pulse Width LOAD Delay from SCL LDAC Pulse Width SRO Output Delay 2-Wire Mode SCL High Time SDA Valid to SCL Hold SCL High Time SCL Low Time SCL Rise Time SCL Fall Time LDAC Pulse Width SCL Valid to SDA Setup SDA Valid to SCL Setup SDA Valid to Rising SCL SRO Output Delay tS1 tS1 tH t1 t2 ns ns ns ns ns s s ns ns ns ns ns ns ns ns s s ns ns ns ns ns
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3
CMOS, Quad, Serial-Interface 8-Bit DAC MAX500
ELECTRICAL CHARACTERISTICS--Single Supply
(VDD = +15V 5%, VSS = AGND = DGND = 0V, VREF = 10V, TA = TMIN to TMAX, unless otherwise noted.) PARAMETER STATIC PERFORMANCE Resolution Total Unadjusted Error Relative Accuracy Differential Nonlinearity Full-Scale Error Full-Scale Tempco VREF = 10V TA = +25C Zero-Code Error TA = TMIN to TMAX MAX500A MAX500B MAX500A MAX500B 30 Guaranteed monotonic MAX500A MAX500B 5 15 20 20 30 SYMBOL CONDITIONS MIN 8 VDD = 15V 5%, VREF = 10V MAX500A MAX500B MAX500A MAX500B 1 2 1/2 1 1 1/2 1 TYP MAX UNITS Bits LSB LSB LSB LSB ppm/C
mV
Zero-Code Tempco REFERENCE INPUT--All specifications are the same as for dual supplies. DIGITAL INPUTS--All specifications are the same as for dual supplies. DYNAMIC PERFORMANCE--All specifications are the same as for dual supplies. POWER SUPPLIES Positive Supply Voltage VDD For specified performance TA = +25C Positive Supply Current IDD Outputs unloaded TA = TMIN to TMAX SWITCHING CHARACTERISTICS--All specifications are the same as for dual supplies. Note 2: Note 3: Note 4: Note 5: Note 6: Note 7:
V/C
14.25
15.75 10 12
V mA
Guaranteed by design. Not production tested. TA = +25C, VREF = 10kHz, 10V peak-to-peak sine wave. LOAD has a weak internal pull-up resistor to VDD. DAC switched from all 1s to all 0s, and all 0s to all 1s code. Sample tested at +25C to ensure compliance. Slow rise and fall times are allowed on the digital inputs to facilitate the use of opto-couplers. Only timing for SCL is given because the other digital inputs should be stable when SCL transitions.
__________________________________________Typical Operating Characteristics
RELATIVE ACCURACY vs. REFERENCE VOLTAGE
MAX500-04
DIFFERENTIAL NONLINEARITY vs. REFERENCE VOLTAGE
DIFFERENTIAL NONLINEARITY (LSB) TA = +25C, VSS = -5V 0.5
MAX500-05
1.0 TA = +25C, VSS = -5V RELATIVE ACCURACY (LSB) 0.5
1.0
VDD = 15V
0
0
-0.5
VDD = 12V
-0.5
VDD = 12V VDD = 15V 0 2 4 6 VREF (V) 8 10 12 14
-1.0 0 2 4 6 VREF (V) 8 10 12 14
-1.0
4
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CMOS, Quad, Serial-Interface 8-Bit DAC
____________________________Typical Operating Characteristics (continued)
MAX500
OUTPUT SINK CURRENT vs. OUTPUT VOLTAGE
MAX500-01
SUPPLY CURRENT vs. TEMPERATURE
MAX500-02
ZERO-CODE ERROR vs. TEMPERATURE
1.5 ZERO-CODE ERROR (mV) 1.0 0.5 0.0 -0.5 -1.0 -1.5 -2.0 VSS = -5V -55 -25 0 25 50 75 100 125 VOUTD VOUTB VOUTA
MAX500-03
16 VSS = -5V 14 12 ISINK (mA) 10 8 6 4 2 0 0 2 4 6 8 RO 200 VSS = 0V
12 10 SUPPLY CURRENT (mA) 8 6 4 2 0 -2 -4 -6 ISS IDD
2.0
VOUTC
10
-55
-25
0
25
50
75
100
125
VOUT (V)
TEMPERATURE (C)
TEMPERATURE (C)
_______________Detailed Description
The MAX500 has four matched voltage-output digital-toanalog converters (DACs). The DACs are "inverted" R-2R ladder networks which convert 8 digital bits into equivalent analog output voltages in proportion to the applied reference voltage(s). Two DACs in the MAX500 have a separate reference input while the other two DACs share one reference input. A simplified circuit diagram of one of the four DACs is provided in Figure 1.
R ... 2R 2R DB0 VREF DB0 AGND DB5 2R
R
R
VOUT
of the V REF inputs is code dependent. The lowest value, approximately 11k (5.5k for VREFA/B), occurs when the input code is 01010101. The maximum value of infinity occurs when the input code is 00000000. Because the input resistance at VREF is code dependent, the DAC's reference sources should have an output impedance of no more than 20 (no more than 10 for VREFA/B). The input capacitance at VREF is also code dependent and typically varies from 15pF to 35pF (30pF to 70pF for V REF A/B). V OUT A, V OUT B, VOUTC, and VOUTD can be represented by a digitally programmable voltage source as: VOUT = Nb x VREF / 256 where N b is the numeric value of the DAC's binary input code.
2R
2R
Output Buffer Amplifiers
All voltage outputs are internally buffered by precision unity-gain followers, which slew at greater than 3V/s. When driving 2k in parallel with 100pF with a full-scale transition (0V to +10V or +10V to 0V), the output settles to 1/2LSB in less than 4s. The buffers will also drive 2k in parallel with 500pF to 10V levels without oscillation. Typical dynamic response and settling performance of the MAX500 is shown in Figures 2 and 3. A simplified circuit diagram of an output buffer is shown in Figure 4. Input common-mode range to AGND is provided by a PMOS input structure. The output circuitry incorporates a pull-down circuit to actively drive VOUT to within +15mV of the negative supply (VSS). The buffer circuitry allows each DAC output to
5
DB5 DB6
DB6 DB7
DB7
... ...
Figure 1. Simplified DAC Circuit Diagram
VREF Input The voltage at the VREF pins (pins 4, 12, and 13) sets the full-scale output of the DAC. The input impedance
_______________________________________________________________________________________
CMOS, Quad, Serial-Interface 8-Bit DAC MAX500
POSITIVE STEP (VSS = -5V or 0V) NEGATIVE STEP (VSS = -5V or 0V)
LDAC 5V/div
LDAC 5V/div
INPUT (5V/div)
OUTPUT 100mV/div
OUTPUT 100mV/div
OUTPUT (20mV/div)
1s/div
1s/div
Figure 2. Positive and Negative Settling Times
DYNAMIC RESPONSE (VSS = -5V or 0V)
LDAC 5V/div
VDD NPN EMITTER FOLLOWER PULL-UP PMOS (-) VOUT CC NMOS ACTIVE PULL-DOWN CIRCUIT VSS
FROM INVERTED DAC OUTPUT (+)
OUTPUT 5V/div
INPUTS
2s/div
Figure 3. Dynamic Response
Figure 4. Simplified Output Buffer Circuit
sink, as well as source up to 5mA. This is especially important in single-supply applications, where V SS is connected to AGND, so that the zero error is kept at or under 1/2LSB (VREF = +10V). A plot of the Output Sink Current vs. Output Voltage is shown in the Typical Operating Characteristics section.
Digital Inputs and Interface Logic
The digital inputs are compatible with both TTL and 5V CMOS logic; however, the power-supply current (IDD) is somewhat dependent on the input logic level. Supply current is specified for TTL input levels (worst case) but is reduced (by about 150A) when the logic inputs are driven near DGND or 4V above DGND. Do not drive the digital inputs directly from CMOS logic running from a power supply exceeding 5V. When driv6
ing SCL through an opto-isolator, use a Schmitt trigger to ensure fast SCL rise and fall times. The MAX500 allows the user to choose between a 3-wire serial interface and a 2-wire serial interface. The choice between the 2-wire and the 3-wire interface is set by the LOAD signal. If the LOAD is allowed to float (it has a weak internal pull-up resistor to VDD), the 2-wire interface is selected. If the LOAD signal is kept to a TTL-logic high level, the 3-wire interface is selected.
3-Wire Interface
The 3-wire interface uses the classic Serial Data (SDA), Serial Clock (SCL), and LOAD signals that are used in standard shift registers. The data is clocked in on the falling edge of SCL until all 10 bits (8 data bits and 2 address bits) are entered into the shift register.
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CMOS, Quad, Serial-Interface 8-Bit DAC MAX500
A1 SCL A0 D7 MSB D6 D5 D4 D3 D2 D1 D0 LSB
SDA
LOAD
LDAC SRO (SERIAL OUTPUT) SCL t2 t1
SCL tH tLDS LOAD tLDW
SDA
tS1
SRO tD1
LDAC tLDS tLDAC
Figure 5. 3-Wire Mode
A1 SCL
A0
D7 MSB
D6
D5
D4
D3
D2
D1
D0 LSB
SDA
LDAC
SRO (SERIAL OUTPUT) t2 SCL tS1 SDA tD1 tS3 SDA tLDS LDAC tLDAC t1 SCL tS2
SRO tD1
Figure 6. 2-Wire Mode
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CMOS, Quad, Serial-Interface 8-Bit DAC
A low level on LOAD line initiates the transfer of data from the shift register to the addressed input register. The data can stay in this register until all four of the input registers are updated. Then all of the DAC registers can be simultaneously updated using the LDAC (load DAC) signal. When LDAC is low, the input register's data is loaded into the DAC registers (see Figure 5 for timing diagram). This mode is cascadable by connecting Serial Output (SRO) to the second chip's SDA pin. The delay of the SRO pin from SCL does not cause setup/hold time violations, no matter how many MAX500s are cascaded. Restrict the voltage at LDAC and LOAD to +5.5V for a logic high.
MAX500
The data is entered into the shift register in the following order: A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 (First) (MSB) (Last) where address bits A1 and A0 select which DAC register receives data from the internal shift register. Table 1 lists the channel addresses. D7 (MSB) through D0 is the data byte. Since LDAC is asynchronous with respect to SCL, SDA, and LOAD, care must be taken to assure that incorrect data is not latched through to the DAC registers. If the 3-wire serial interface is used, LDAC can be either tied low permanently or tied to LOAD as long as tLDS is always maintained. However, if the 2-wire interface is used, LDAC should not fall before the stop condition is internally detected. (This is the reason for the t LDS delay of LDAC after the last rising edge of SDA.)
2-Wire Interface
The 2-wire interface uses SDA and SCL only. LOAD must be floating or tied to VDD. Each data frame (8 data bits and 2 address bits) is synchronized by a timing relationship between SDA and SCL (see Figure 6 for the timing diagram). Both SDA and SCL should normally be high when inactive. A falling edge of SDA (while SCL is high) followed by a falling edge of SCL (while SDA is low) is the start condition. This always loads a 0 into the first bit of the shift register. The shift register is extended to 11 bits so this "data" will not affect the input register information. The timing now follows the 3wire interface, except the SDA line is not allowed to change when SCL is high (this prevents the MAX500 from retriggering its start condition). After the last data bit is entered, the SDA line should go low (while the SCL line is low), then the SCL line should rise followed by the SDA line rising. This is defined as the stop condition, or end of frame. Cascading the 2-wire interface can be done, but the user must be careful of both timing and formatting. Timing must take into account the intrinsic delay of the SRO pin from the internally generated start/stop conditions. The tS2 value should be increased by n times tD1 (where n = number of cascaded MAX500s). The tLDS value should also be increased by n times tD1. No other timing parameters need to be modified. A more serious concern is one of formatting. Generally, since each frame has a start/stop condition, each chip that has data cascaded through it will accept that data as if it were its own data. Therefore, to circumvent this limitation, the user should not generate a stop bit until all DACs have been loaded. For example, if there are three MAX500s cascaded in the 2-wire mode, the data transfer should begin with a start condition, followed by 10 data bits, a zero bit, 10 data bits, a zero bit, 10 data bits, and then a stop condition. This will prevent each MAX500 from decoding the middle data for itself.
Table 1. DAC Addressing
A1 L L H H A0 L H L H SELECTED INPUT REGISTER DAC A Input Register DAC B Input Register DAC C Input Register DAC D Input Register
Table 2. Logic Input Truth Table
SCL F H L F H L H H SDA Data Data X Data X X X X LOAD LDAC VDD VDD VDD M M M L L H H H H H H H L FUNCTION Latching data into shift register (2W) Data should not be changing (2W) Data is allowed to change (2W) Latching data into shift register (3W) Data is allowed to change (3W) Data is allowed to change (3W) Loads input register from shift register (3W) DAC register reflects data held in their respective input registers
Notes: H = Logic High L = Logic Low M = TTL Logic High X = Don't Care
2W = 2-Wire 3W = 3-Wire F = Falling Edge
8
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CMOS, Quad, Serial-Interface 8-Bit DAC
The SRO output swings from VDD to DGND. Cascading to other MAX500s poses no problem. If SRO is used to drive a TTL-compatible input, use a clamp diode between TTL +5V and VDD and the current-limiting resistor to prevent potential latchup problems with the 5V supply. Table 2 shows the truth table for SDA, SCL, LOAD, and LDAC operation. Figures 5 and 6 show the timing diagrams for the MAX500. ground buses within one diode drop of each other. To avoid parasitic device turn-on, AGND must not be allowed to be more negative than DGND. DGND should be used as supply ground for bypassing purposes.
MAX500
REFERENCE INPUTS 4 12 13 VREFA/B VREFC VREFD DAC A
__________Applications Information
Power-Supply and Reference Operating Ranges
The MAX500 is fully specified to operate with V DD between +12V 5% and +15V 10% (+11.4V to +16.5V), and with VSS from 0V to -5.5V. 8-bit performance is also guaranteed for single-supply operation (VSS = 0V), however, zero-code error is reduced when VSS is -5V (see Output Buffer Amplifiers section). For an adequate DAC and buffer operating range, the VREF voltage must always be at least 4V below VDD. The MAX500 is specified to operate with a reference input range of +2V to VDD - 4V.
+15V 14 VDD 2
VOUTA
1 DAC B DIGITAL INPUTS NOT SHOWN DAC C VOUTB
16 VOUTC
15 DAC D VSS 3 -5V (OR GND) AGND 5 DGND 6 VOUTD
Ground Management
Digital or AC transient signals between AGND and DGND will create noise at the analog outputs. It is recommended that AGND and DGND be tied together at the DAC and that this point be tied to the highest quality ground available. If separate ground buses are used, then two clamp diodes (1N914 or equivalent) should be connected between AGND and DGND to keep the two
SYSTEM GND
MAX500
Figure 8. MAX500 Unipolar Output Circuit
VOUTB VOUTA VSS VREFA/B
AGND DGND
VOUTC VOUTD VDD VREFC VREFD
VREF
R1
R2
+15V DAC OUTPUT FROM MAX500 -15V R1 = R2 = 10k 0.1% VOUT
COMPONENT SIDE (TOP VIEW)
NOTE: VREF IS THE REFERENCE INPUT FOR THE MAX500
Figure 7. Suggested MAX500 PC Board Layout for Minimizing Crosstalk
Figure 9. Bipolar Output Circuit
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9
CMOS, Quad, Serial-Interface 8-Bit DAC MAX500
Table 3. Unipolar Code Table
DAC CONTENTS MSB 1111 LSB 1111 ANALOG OUTPUT +VREF 255 256 +VREF 129 256 +VREF 128 256 +VREF
Table 4. Bipolar Code Table
DAC CONTENTS MSB 1111 LSB 1111 ANALOG OUTPUT +VREF 127 128 +VREF
(----)
(----)
1 (----) 128
1000
0001
(----)
V
1000 1000 0111
0001 0000 1111
1000
0000
REF (----) = + ---- 2
0V -VREF -VREF 1 (----) 128 127 (----) 128
0111
1111
(----) 256
0000 0001
127
0000 0000
0001 0000 1 ( --- ) 256
1 +VREF 256 0V
(----)
0000 0000 Note: 1LSB = (VREF) (2-8) = +VREF 1 ( --- ) 256
-VREF 128 128
(----) = -VREF
Note: 1LSB = (VREF) (2-8) = +VREF
Careful PC board ground layout techniques should be used to minimize crosstalk between DAC outputs, the reference input(s), and the digital inputs. This is particularly important if the reference is driven from an AC source. Figure 7 shows suggested PC board layouts for minimizing crosstalk.
+15V 4 VREFA/B 14 VDD
Unipolar Output
In unipolar operation, the output voltages and the reference input(s) are the same polarity. The unipolar circuit configuration is shown in Figure 8 for the MAX500. The device can be operated from a single supply with a slight increase in zero error (see Output Buffer Amplifiers section). To avoid parasitic device turn-on, the voltage at V REF must always be positive with respect to AGND. The unipolar code table is given in Table 3.
+ VIN 5 + VBIAS AGND
2 DAC A
VOUTA
MAX500
VSS 3 -5V (OR GND) DIGITAL INPUTS NOT SHOWN DGND 6
Figure 10. AGND Bias Circuit
Bipolar Output
Each DAC output may be configured for bipolar operation using the circuit in Figure 9. One op amp and two resistors are required per channel. With R1 = R2: VOUT = VREF (2DA - 1) where DA is a fractional representation of the digital word in Register A. Table 4 shows the digital code versus output voltage for the circuit in Figure 9.
Offsetting AGND
AGND can be biased above DGND to provide an arbitrary nonzero output voltage for a "zero" input code. This is shown in Figure 10. The output voltage at VOUTA is: VOUTA = VBIAS + DAVIN where DA is a fractional representation of the digital input word. Since AGND is common to all four DACs, all outputs will be offset by VBIAS in the same manner. Since AGND current is a function of the four DAC codes, it should be driven by a low-impedance source. VBIAS must be positive.
10
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CMOS, Quad, Serial-Interface 8-Bit DAC
Using an AC Reference
In applications where VREF has AC signal components, the MAX500 has multiplying capability within the limits of the VREF input range specifications. Figure 11 shows a technique for applying a sine-wave signal to the reference input, where the AC signal is biased up before being applied to VREF. Output distortion is typically less than 0.1% with input frequencies up to 50kHz, and the typical -3dB frequency is 700kHz. Note that VREF must never be more negative than AGND.
MAX500
+15V 15k AC REFERENCE INPUT 10k VOUTB 1 VOUTB -4V DAC B
4 VREFA/B
14 VDD
+4V
Generating VSS The performance of the MAX500 is specified for both dual and single-supply (VSS = 0V) operation. When the improved performance of dual-supply operation is desired, but only a single supply is available, a -5V VSS supply can be generated using an ICL7660 in one of the circuits of Figure 12. Digital Interface Applications
Figures 13 through 16 show examples of interfacing the MAX500 to most popular microprocessors.
VSS 3 -5V (OR GND) DIGITAL INPUTS NOT SHOWN
AGND 5
MAX500 DGND 6
Figure 11. AC Reference Input Circuit
12V to 15V 10k 2N2222 2 CAP+ 8 6V ZENER 10k 10F 3 GND V+
10F 4 CAP+5V LOGIC SUPPLY 8 2 CAP+ V+
10F 4 CAP-
ICL7660 VOUT 5
-5V VSS OUT 10F
3
ICL7660 VOUT 5
GND
-5V VSS OUT 10F
Figure 12. Generating -5V for VSS
80C51
P1.0 P1.1 P1.2 P1.3 . . . . . . . SCL SDA
A15
MAX500
SRO VOUTA VOUTB VOUTC VOUTD VREFA/B VREFC VREFD
A0
ADDRESS BUS A1 EN ADDRESS CODE A0 B/A Z8420 C/D B0 CE B1 RD B2 INT B3 . . D7 D0 SCL MAX500 SDA LDAC LOAD*
Z80
I/O REQ WR INT
LDAC LOAD*
D7 D0
DATA BUS
* CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR CONNECT LOAD TO VDD FOR 2-WIRE MODE
* CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR CONNECT LOAD TO VDD FOR 2-WIRE MODE
Figure 13. 80C51 Interface
Figure 14. Z-80 with Z8420 PIO Interface
11
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CMOS, Quad, Serial-Interface, 8-Bit DAC MAX500
A15 A8
ADDRESS BUS A0 82C55 PA0 A1 PA1 CS PA2 WR D7 D0 PA3 . . SCL SDA LDAC LOAD*
MAX500
A15 A0
ADDRESS BUS
8085/ 8088
WR ALE AD7 AD0 EN LATCH
ADDRESS DECODE
6809/ 6502
R/W OR E
ADDRESS DECODE
6821 6521 PA0 C32 PA1 R/W PA2 E DB7 PA3 . . DB0
SCL SDA LDAC LOAD*
MAX500
ADDRESS AND DATA BUS
7 D0
DATA BUS
* CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR CONNECT LOAD TO VDD FOR 2-WIRE MODE
* CONNECT LOAD TO P1.3 FOR 3-WIRE MODE OR CONNECT LOAD TO VDD FOR 2-WIRE MODE
Figure 15. 8085/8088 with Programmable Peripheral Interface
Figure 16. 6809/6502 Interface
____Pin Configurations (continued)
TOP VIEW
20 V OUT C 19 V OUT D 2 V OUT B 3 V OUT A 1 N.C.
___________________Chip Topography
V OUT B V ss V OUT A V OUT D V DD V OUT C
V SS 4 V REF A/B 5 AGND 6 N.C. 7 N.C. 8
18 V DD 17 V REF C
V REF B V REF A AGND
V REF C V REF D 0.159" (4.039mm) SRO
MAX500
16 V REF D 15 SRO 14 N.C.
LDAC 10
SDA 11
LOAD 12
SCL 13
9
DGND
DGND
SDA SCL LOAD LDAC 0.150" (3.810mm)
LCC
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
12 __________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 (408) 737-7600 (c) 1996 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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